Tour of TSMC at Taiwan

Designing the Intelligent software using ARMv8(64bit-1st Generation) architecture. Next Generation(128bit-Huge Cache). The birth of intelligent devices with basic instruction sets, minimum 7″ display to display huge cache of data.
http://en.wikipedia.org/wiki/ARM_architecture

Released in late 2011, ARMv8 represents the first fundamental change to the ARM architecture. It adds a 64-bit architecture, dubbed ‘AArch64’, and a new ‘A64’ instruction set. Within the context of ARMv8, the 32-bit architecture and instruction set are referred to as ‘AArch32’ and ‘A32’, respectively. The Thumb instruction sets are referred to as ‘T32’ and have no 64-bit counterpart. ARMv8 allows 32-bit applications to be executed in a 64-bit OS, and for a 32-bit OS to be under the control of a 64-bit hypervisor.[1] As of March 2012, only the ARMv8-A (“application”) profile has been defined, and no implementations have been announced.

To both AArch32 and AArch64, ARMv8 makes VFP and advanced SIMD (NEON) standard. It also adds cryptography instructions supporting AES and SHA-1/SHA-256.

AArch64 features:

New instruction set, A64
31 general-purpose 64-bit registers
Instructions are still 32 bits long and mostly the same as A32
Most instructions can take 32-bit or 64-bit arguments
Addresses assumed to be 64-bit
A new exception system
Fewer banked registers and modes
Memory translation from 48-bit virtual addresses based on the existing LPAE, which was designed to be easily extended to 64-bit

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Author: Gilbert Tan TS

IT expert with more than 20 years experience in Apple, Andriod and Windows PC. Interests include hardware and software, Internet and multimedia. An experienced Real Estate agent, Insurance agent, and a Futures trader.

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